듀얼 FPU와 열전도 지연 공간을 활용한 저온도 마이크로프로세서 구조 설계

Abstract

As the process technology scales down, the microprocessor performance improves but we face thermal problems due to the increased power density caused by the increase in the number of transistors. To solve thermal problems effectively, Dynamic Thermal Management (DTM) has been proposed and has been used to balance thermal reliability and cooling cost. However, the DTM introduces the problem of slowing down the microprocessor because dynamic voltage and frequency scaling, dynamic voltage scaling and instruction fetch throttling are applied. In this thesis, we propose the utilization of dual floating-point adder units to deal with thermal problems while minimizing the performance loss for the floating-point applications. Only one of two floating-point adder units is used selectively in the proposed architecture, resulting in the reduction of the peak temperature in the microprocessor. Temperature has become a key constraint on the microprocessor performance. Activity migration, which enables moving computation between multiple replicated units, can be a solution for reducing peak junction temperature. Activity migration techniques can be divided into two categories: Static activity migration and dynamic activity migration. In static activity migration, the toggling time for each computation unit is fixed. Static activity migration requires simple hardware support but it cannot react to thermal emergencies effectively due to the fixed operation time per unit. On the contrary, in dynamic activity migration, the toggling time is decided dynamically based on the information from the digital thermal sensor such that thermal problems can be handled as they are detected by the sensor and comparator. We also propose a new floorplanning technique, which includes a Heat Conduction Delay Space (HCDS) in the microprocessor for overcoming the thermal problem of Heat Conduction between adjacent hot units. To estimate the temperature with these proposed schemes, we extended the DTM version by modifying the Wattch, HotSpot, and hotfloorplan tools. From the experiments, we show that the peak temperature drops by 5.3℃ on the average (maximum 10.8℃) for the microprocessor where the DTM with dual FPU and Heat Conduction delay space is utilized. In addition, we show that the performance of the microprocessor is improved by 45% on the average by reducing the stall time due to the DTM.