JPEG2000 CODEC을 위한 Tier-1 코딩 알고리즘의 VLSI 구현

Abstract

The development and diversification of computer networks as well as the emergence of new imaging applications have highlights various shortcomings in classic image compression standards, such as JPEG. Consequently the JPEG Committee decided to develop a new image compression algorithm : JPEG2000. This standard has a much higher compression efficiency and enables inherently various features such as lossy or lossless encoding, resolution and quality scalability, regions of interest, error resilience. In this paper, we have proposed a encoder architecture to perform the JPEG2000 part Ⅰ standard for compression images. The architecture consists of modules to implement the lifting based DWT(Discrete Wavelet Transform), BPC(Bit Plane Coder), and BAC(Binary Arithmetic Coder) algorithms and memory interfacing modules. Three pairs of BPC and BPC modules are used to reduce the time required for entropy coding. The parallel mode is adopted to BPC coder to increase encoding efficiency between each coding pass. The Tier-1 EBCOT encoder has been implemented with VHDL. And it is implemented using FPGA(Altera Cyclone Ⅱ and PXA255 processor). It takes about 89% of the chip area and the estimated frequency of operation is 45Mhz. Therefore, It can be easily be adapted to satisfy various formats from Digital Cinema.