CMOS 단일 전원 OP AMP 설계

Abstract

The research is based on hearing aids specialized CMOS analog integrated chip (IC) design. The hearing aids IC design faces the challenges from the constraints of its special applications on In-The-Ear (ITE) hearing aids. Firstly, The chip works on a single supply voltage of 1.3V. With the single supply, or we may say a single battery, the hearing aid can be made small enough to be completely put into the ear canal. Secondly, a low power dissipation is required. It makes the battery lasts longer, gets less thermal noise, etc. The efforts on solutions to the two issues can be found on different areas. In this thesis, I tried short channel processes in order to get a low supply as well as a low power consumption. I tried two different short channel processes, ANAM-0.18um and Samsung-0.18um. Two design methods, a optimization design and a transistor scale ratio design were also introduced. These methods achieve a high accuracy and efficiency on the prediction of deep-submicron device circuit parameters.