다층구조의 절연향상을 위한 산화막 평탄화 특성 개선

Abstract

CMP process is effectively used to flat dielectric layer such as IMD, ILD, PMD and metal layer such as W, Al, Cu in order to perform multi layer structure of deep sub micron integrated circuit. It is also done to make various devices and new materials. Recently as speed of semiconductor gets higher and integration capacity gets bigger, multi—layer interconnection technique becomes important problem in sub micron process. Especially, decrease of wavelength related to the source of light is necessary to perform minute pattern in the process technique under 0.35um. As the wavelength decreases, resolution is improved but depth of focus decreases, which brings unflatize in multi layer process. There are two methods in the conventional process. The first method is to employ Etch-Back after making oxidation film with high liquidity, reflow, and then RP coating. The second method is heat treatment after spin coating of volatile macromolecule materials, SOG and reflow. But the method was only partial flatization and so it can not satisfy global flatization-technical requirement. As the aluminum wiring materials has been replaced by copper and wiring materials with low-K have been developed, the new process-CMP can flat globally. Since 1980 the method has been used by IBM. Chemical and manufacturing remaining of wiring metals in the scratch can be entered. Especially in the case the scratch come into being in the gap of wiring and if scratch exits between wirings. serious effects can be incurred. For getting good characteristics of devices, it is assumed that another materials such as scratch and slurry on the surface of dielectric and metal layer should not be remained. Because dual damascence method performed one CMP instead of dual CMP by the ordinary damascence method, it is characteristic of lowering the occurrence of process defects. Oxide CMP process has been well accepted for the planarization of the dielectric oxide film and becomes a critical process in ULSI manufacturing due to the rapid shrinkage of the design rule for the device [1]. But CMP process generates defects inevitably such as micro-scratch, pit, and polishing residue. As the design rule becomes smaller and smaller, among these defects micro-scratches cause severe circuit failure, the reduction of durability and reliability and the increase of current leakage in semiconductor [2]. It is important to develop post CMP cleaning process to observe scratches since they are not easy to detect on flat oxide surfaces [3]. CMP process is effectively used to flat dielectric layer such as IMD, ILD, PMD and metal layer such as W, Al, Cu in order to perform multi layer structure of deep sub micron integrated circuit. CMP process has been known to have a significant effect on the global planarization of multi-level interconnection structure. However, there are many practical problems in application due to the synchronicity of mechanical and chemical polishing. One of the most critical problems is the higher cost of consumables (COC) such as pad, slurry, backing film, and pad conditioner which accounts for over 70 % of cost of ownership (COO). In this paper, we have investigate the possibility of mixed abrasive slurry such as ZrO2, CeO2, and MnO2 for the oxide CMP application.