Improving IEEE 1588v2 Time Synchronization Performance with Phase Locked Loop

Abstract

Time synchronization holds a very important matter in communication. Several approaches have been proposed in order to reduce PDV (Packet Delay Variation). PDV consists of several possible sources such as queuing delay, processing delay, and transmission delay. However, the last two sources can be ignored since they are only contributing a few micro seconds to the offset accuracy. However, the queuing delay is become a big problem of offset accuracy, since it is unpredictable, and possible to have a very big value. Moreover, there is another factor that should be considered, which is the difference of the clock frequency in every device. In this thesis, we analyze IEEE 1588 and PLL. Then, we propose a method that is capable to mitigate the error from the queuing delay and the clock drift. Our simulation results show that our proposed method can reduce the PDV to the network requirement. However, this type of method only works for several types of clock, and then in order to use PLL for all type of clock is still a challenge